This invention relates to a semiconductor device capable of being made thin and having a high reliability and a manufacturing method therefor.
In recent years, semiconductor devices are being made small-sized and multi-pin in order to be miniaturized and multi-functioned. FIG. 26a is a perspective view of a semiconductor device proposed for realizing miniaturization, and FIG. 26b is a fragmental sectional view of a portion around an external connection electrode of this semiconductor device. In FIGS. 26a and 26b, on a surface of a semiconductor substrate 1 on which an electrical circuit (not shown) is formed, a bonding pad 2 made of an aluminum alloy or the like for an external connection and an electrically insulating film 3 made of SiN, SiO or the like for electrical circuit protection are formed. On the bonding pad 2 on the semiconductor substrate 1, an intimate contact layer and a diffusion protection layer are provided. Also provided in this semiconductor device are substrate metal layer 4 composed of a plurality of metal layers, a protective layer 5 made of polyimide or the like and having an opening at a region corresponding to the substrate metal layer 4 for external connection, transfer bumps 7 formed by transferring electrodes formed on the substrate (not shown), encapsulating resin 8 encapsulating all of the above-mentioned components 1 to 7, and external electrodes 9 for external connection.
Since the external electrodes 9 are provided on the semiconductor substrate 1 in the above semiconductor device 1, a very small semiconductor device in which only the thickness of the encapsulating resin 8 is increased can be realized on the semiconductor substrate 1.
FIGS. 27a to 27e are sectional views illustrating the steps of a semiconductor device manufacturing method disclosed in Japanese Patent Laid-Open No. 1-179334. The manufacturing steps will now be described in conjunction with these FIGS. 27a to 27e. First, as shown in FIG. 27a, a resist 11 with a pattern therein is formed on a transferring substrate 10 made of copper, aluminum, stainless steel or the like and having a thickness of the order of 0.1 mm to 3 mm, and a lead pattern 12 made of copper, aluminum or the like having a thickness of the order of 5 .mu.m to 50 .mu.m is formed in the openings by electrolytic plating, for example. Then, as shown in FIG. 27b the semiconductor substrate 1 is bonded on the lead pattern 12 by means of an electrically conductive bonding material 13, such as solder, an electrically conductive paste or the like. This is further entirely covered by the encapsulating resin 8 as shown in FIG. 27c. Then, by removing the transferring substrate 10, the semiconductor device shown in FIG. 27d is obtained. If desired, as shown in FIG. 27e, the lead pattern 12 may be extended outwardly of the encapsulating resin 8 so as to be adapted to the bonding position on the circuit board on which the semiconductor device is to be mounted.
FIG. 28 is a sectional view of the semiconductor device disclosed in Japanese Patent Laid-Open No. 5-283460. In this semiconductor device, a lead pattern 12 is disposed on an electrically insulating base film 14 and a semiconductor substrate 1 is encapsulated on the base film 14 with an encapsulating resin 8. The lead pattern 12 is exposed at the openings of the base film 14 at which an external connection electrodes 15 are formed.
Further, when high density wiring and good electrical characteristics (a low dielectric factor) are required in packages such as a pin grid array (PGA), ball grid array (BGA) or the like, a thin film, multi-layered laminated substrate has been used. FIG. 29 is a sectional view of a semiconductor device utilizing a conventional organic material multi-layered laminated substrate. In the figure, the reference numeral 31 is a semiconductor element, 32 are projection electrodes of the semiconductor element 31, 33 is a core substrate, 34 are laminated wiring layers, and 35 are internal electrode pads on the surface layer of the laminated wiring layers 34 connected to the projection electrodes. The reference numeral 36 is a wiring inside of the laminated wiring layers 34, 37 is an electrically insulating layer made, for example, of polyimide, 38 is a through hole for electrically connecting the obverse and the reverse surfaces of the core substrate 33 made, for example, of glass epoxy, 39 are external electrode pads, 40 are solder balls attached to the external electrode pads 39, 41 is a mold resin for encapsulating the semiconductor element 31 and 42 is a solder resist covering the wiring on the surface layer with the internal electrode pads 35 exposed.
The operation of the above conventional device will now be described. The electrical power and the external signals are supplied from the land of the mounting board on which the semiconductor device is mounted to the external electrode pads 39 through the solder balls 40, and transmitted to the wiring 36 of the laminated wiring layer 34 on the reverse side of the core substrate 33 and further through the through holes 38 of the core substrate 33 to the wiring 36 of the laminated wiring layer 34 on the obverse side of the core substrate 33. The signals are further transmitted from the wiring 36 to the semiconductor element 31 through the internal electrode pads 35 and the projection electrode 32. The outputs from the semiconductor element 31 are transmitted to the external circuit through the same passage in the reverse order.
FIG. 30 is a sectional view showing a conventional semiconductor device, in which the reference numeral 61 is a semiconductor substrate, 62 is a wiring, 63 are metal wires connecting the semiconductor substrate 61 and the wiring 62, 64 is a core substrate, 65 are through holes provided in the core substrate 64, 66 are solder balls attached to the bottom surface of the core substrate 64 through external electrode lands 67 and 68 is an encapsulating resin. In the conventional semiconductor device shown in FIG. 26, similar to the device shown in FIG. 27, there is a problem in that not very many external electrodes can be provided on the semiconductor device because the external electrodes can be attached only to the bottom surface of the semiconductor substrate.
Also, in the conventional semiconductor device shown in FIG. 27, the lead pattern 12 is formed on the transferring substrate 10, and the lead pattern 12 and the semiconductor substrate 1 are bonded to transfer the lead pattern 12 to the semiconductor substrate 1 which then is covered and encapsulated with the resin. However, in this device, since the section to which the external electrodes are to be formed is provided only on the bottom surface of the semiconductor substrate 1, it is not possible to provide a large number of external electrodes.
In the example shown in FIG. 28, the lead pattern 12 is provided on the base film 14, so that the thickness of the base film 14 may raise a problem in decreasing the overall thickness of the semiconductor device.
Further, in the package shown in FIG. 29 in which the conventional multi-layered laminated substrate made of an organic material is used, the semiconductor element is mounted to the substrate having a laminated wiring layer on either or both surfaces of the core substrate and is provided with external electrode pads on the surface of the substrate opposite to the surface on which the semiconductor element is mounted and resin coated. The signal from the semiconductor element is transmitted to an external electrode through the through holes in the core substrate. With such a structure, since the through holes are not flat at their top portions, the formation of the wiring on the through hole is difficult and discontinuous or narrowed sections may be formed. Therefore, in the usual design, the wiring is not formed on the through holes, so that the wiring density becomes low and impedes the miniaturization of the package.
Also in the device shown in FIG. 29, the core substrate or the substrate of the organic material such as glass epoxy has a structure of resin-impregnated woven glass fiber for mechanical strength, so that the migration of wiring material, Cu can take place along the interface between the glass fiber and the resin, causing leakage between the through holes. Therefore, a quad flat pack (QFP) type package, in which the external leads extend only from the outer periphery of the substrate instead of providing the external electrodes on the bottom surface of the substrate, is generally used. In order to cope with this problem. A ceramic substrate may not need through holes in the core substrate. However, with the ceramic substrate, the thermal expansion coefficient does not match with the plastic mounting substrate such as glass epoxy which is commonly used in electronic devices causing stresses to be applied to the solder balls of the external electrodes, decreasing the reliability of the mounting and packaging.
A laminated substrate which does not use a core substrate can be obtained In accordance with the manufacturing method of a laminated substrate in which a plurality of wired films of an organic material is disclosed in Japanese Patent Laid-Open No. 3-250649 and Japanese Patent Laid-Open No. 5-226509. However, since the device does not have a sufficient rigidity because there is no core substrate, errors may occur during the package manufacturing process in the wire bonding step in which the rigidity of the substrate is required and in the flip chip bonding step in which flatness of the substrate is required. Also, the internal electrode pads may become displaced from the designed pitch due to the dimensional instability of the film of the organic material. Further, in the manufacturing method of Japanese Patent Laid-Open No. 3-250649 and Japanese Patent Laid-Open No. 5-226509, since the film of each layer does not include reinforcing material for providing mechanical strength, such as woven glass fiber, woven carbon fiber or the like, the film can be easily deformed so that it is necessary to have a thickness of at least several tens .mu.m or more, whereby a thin substrate cannot be obtained.
Also, in the conventional device shown in FIG. 30, the core substrate 64 is provided for package rigidity for forming wiring 64, so that the thickness of the package is increased by the thickness of the core substrate 64, preventing decrease of the thickness. Further, while the core substrate 64 has formed therein through holes 65 for the electrical connection between the wiring 62 and the external electrodes, the problem of leakage between the through holes 65 may occur and reliability decreased.